Conventional multi junction solar cells have been widely used for terrestrial and space applications because of their high efficiency. Multijunction solar cells (100), as shown in FIG. 1, include multiple diodes in series connection, known in the art as junctions or subcells (106, 107, and 108), realized by growing thin regions of epitaxy in stacks on semiconductor substrates. Each subcell in a stack possesses a unique bandgap and is optimized for absorbing a different portion of the solar spectrum, thereby improving efficiency of solar energy conversion. These subcells are chosen from a variety of semiconductor materials with different optical and electrical properties in order to absorb different portions of the solar spectrum. The materials are arranged such that the bandgap of the subcells becomes progressively narrower from the top subcell (106) to the bottom subcell (108). Thus, high-energy photons are absorbed in the top subcell and less energetic photons pass through to the lower subcells where they are absorbed. In every subcell, electron-hole pairs are generated and current is collected at ohmic contacts in the solar cell. Semiconductor materials used to form the subcells include, but are not limited to, germanium and alloys of one or more elements from group III and group V on the periodic table. Examples of these alloys include, but are not limited to, indium gallium phosphide, indium phosphide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, and dilute nitride compounds. For ternary and quaternary compound semiconductors, a wide range of alloy ratios can be used.
Solar cells are manufactured on a wafer scale using conventional semiconductor processing methods known to practitioners skilled in the art. Danzilio (CS MANTECH Conference, May 14-17, 2007, Austin, Tex., pp. 11-14) summarizes the processing steps for making a typical multijunction solar cell.
A through-wafer via (TWV) is an electrical interconnect between the top (front) and bottom (back) surfaces of a semiconductor chip. TWVs are routinely used for a variety of applications in the field of semiconductor devices including solar cells. FIG. 2A and FIG. 3A show examples of TWVs (200 and 300) for solar cells with front and back contacts. TWVs are electrically isolated from the solar cell substrate (202 and 302) and all the epitaxial regions (203 and 303), and are electrically connected to the patterned cap regions (204 and 304). The patterned cap regions are patterned such that they surround the TWV structures on the top surface of the solar cell. Front side metal pads (201 and 301) lay over patterned cap regions (204 and 304). TWVs also comprise back side metal (205 and 305), via metal (206 and 306), passivation layer (207 and 307), via contact metal region (208 and 308) and gap 209 between passivation layer 207 and back side metal 205. In some known examples of TWVs, a recess structure 309 is present in the TWV design. Methods to fabricate TWVs are known to practitioners skilled in the art of semiconductor fabrication. For example, Chen et al. (Journal of Vacuum Science and Technology B, Volume 27, Issue 5, p. 2166-2009) disclose a semiconductor device with TWVs for a high mobility electron transport device application.
TWVs are also used to provide back-contact packaging in solar cells. Back-contact cells have both positive and negative external contact pads disposed on the back surface, which allows for optimized module efficiency by increasing the packing density of solar cells. Shading losses and resistive losses are also significantly reduced. Van Kerschaver et al. (Progress in Photovoltaics: Research and Applications 2006; 14:107-123) summarizes several approaches for back-contact solar cells.
Dry etching is a routine method used in semiconductor fabrication which has found limited use in solar cell manufacturing. Dry etching involves the removal of semiconductor material by exposing the material to plasma of reactive gases in a vacuum chamber. Dry etching of heteroepitaxial layers in multijunction solar cells involves added complexity because each class of semiconductor material requires a unique etch condition. This complexity causes a slower net etch rate and a bottleneck in manufacturing. As etching proceeds across multiple layers of heterogeneous semiconductor materials, re-deposition of etched-off material causes rough sidewalls and is unavoidable. A mask is used to protect wafer areas where etching is not required. A photosensitive polymer is typically used as the mask, but a photosensitive polymer mask cannot withstand the long etch times and high heat required for dry etching. The photosensitive polymer mask is often destroyed, leading to pitting and significantly to the generation of rough surfaces, which complicates subsequent sidewall passivation processing and decreases reliability of manufactured devices. FIG. 4A depicts a schematic of a wafer cross-section imaged by scanning electron microscopy, damaged with pitting and rough sidewall surfaces (408 and 409). The device shown in FIG. 4A includes cover glass 407, front side metal pad 406, ARC 405, heteroepitaxial layer 403, substrate 402, patterned cap regions 404, and back side 401 of substrate 402. The sidewall 409 of heteroepitaxial layer 403 is characterized by a rough surface including pitting and/or undercutting resulting from the dry etch. Pitting 408 is also shown on the back side surface 401 of substrate 402, which can also be caused by the dry etch. Alternative masking methods such as dielectric hard masks can be used in place of a photosensitive polymer, but these masks require elaborate downstream steps for removal from the wafer. Dry etching also involves expensive equipment setup and maintenance. In summary, dry etching involves the following complications:                1. electroplating or electrografting to protect wafer areas where etching is not desired, requiring expensive and specific equipment;        2. low processing throughput and longer processing time because dry etching can be carried out on only a few wafers at a time;        3. difficulty in controlling etch rate as well as etch stop, leading to insufficient etching or over-etching;        4. uneven etching of heteroepitaxial III-V semiconductor layers results in pitting and rough sidewall surfaces, which complicate subsequent sidewall passivation;        5. higher possibility of device failure due to insufficient sidewall passivation;        6. more chemical, water, and energy consumption during fabrication; and        7. higher cost from equipment procurement and maintenance.        
Wet etching, another method for removing semiconductor material by using chemicals in liquid phase, is not without shortcomings. Typically, wet etchants used for etching one class of semiconductor materials is selective and will not etch certain other classes of semiconductor materials. A comprehensive list of wet etchants, etch rates and selectivity relationships was published by Clawson, Materials Science and Engineering, 31 (2001) 1-438. The selectivity of a wet etchant may also depend on alloy concentration of the compounds. Consequently, etching heteroepitaxial layers can require application of multiple wet etch chemistries. Using multiple applications of different wet etchants due to selectivity typically results in jagged, non-smooth, and/or irregular through-wafer via sidewalls (as shown in FIG. 4A). This is observed in solar cell fabrication where different etch chemistries are used for each class of semiconductor material in the heteroepitaxial layers, resulting in distinctively different etch profiles and rough sidewall surfaces throughout the wafer. Zaknoune et al., J. Vac. Sci. Technol. B 16, 223 (1998) reported a wet etching method that is nonselective for III-V phosphides and arsenides as an alternative to using multiple wet etchants. Although the method is nonselective, the etching of gallium arsenide results in very rough morphology and involves an etch rate 10 times greater than the etching of aluminum gallium indium phosphide. Zaknoune et al. describes a system with one layer of epitaxy, such as that found in heterojunction bipolar transistors (HBT), quantum well lasers (QWL) and high electron mobility transistors (HEMT). The Zaknoune et al. method does not address any sidewall problem related to heteroepitaxial layers that is characteristic of multijunction solar cells.
Typically, rough/jagged through-wafer via sidewalls complicate subsequent sidewall passivation, leading to an increase in device failures and lower fabrication yield. In addition, the use of multiple etchants has other disadvantages compared to single-etch chemistries, including, for example:                1. increased difficulty in controlling the etch rate and undesirable lateral undercutting of layers;        2. uneven etching of different semiconductor layers and increased difficulty in subsequent sidewall passivation processing;        3. higher possibility of device failure due to insufficient sidewall passivation;        4. longer processing time due to complications and unpredictability inherent in the method;        5. more chemical, water, and energy consumption during fabrication; and        6. more chemical waste generation.        
The abovementioned conventional processes have hindered cost-effective fabrication of multijunction solar cells. There were attempts to explore non-selective etchants and a couple examples are briefly described. Zaknoune et. al. (J. Vac. Sci. Technol. B 16, 223, 1998) reports an etching procedure that is nonselective for gallium arsenide and aluminum gallium indium phosphide, where the aluminum gallium indium phosphide quaternary compound has 35% aluminum phosphide, 15% gallium phosphide, and 50% indium phosphide. The etching procedure described by Zaknoune et al. uses a diluted solution of hydrochloric acid, iodic acid, and water to etch 300 nm of the quaternary compound grown on a gallium arsenide substrate using a photosensitive polymer mask. The main application areas described in the paper by Zaknoune et al. are heterojunction bipolar transistors (HBT), various quantum well lasers (QWL), and high electron mobility transistors (HEMT) for which large conduction and valance band discontinuities are required. These devices are majority carrier devices in which the large bandgap materials are typically used as barrier materials for majority carriers. Zaknoune et al. describes a system with one layer of epitaxy and do not recognize any sidewall problem related to multilayer epitaxy that is characteristic of solar cells.
The device requirements for multijunction solar cells are significantly different than for HBTs, QWLs, and HEMTs, largely because multijunction solar cells are minority carrier devices. Consequently the procedure described by Zahnoune et al. has no direct application to etching multijunction solar cell structures, which include a wide variety of semiconductor materials with a wide range of bandgaps (for example, from 0.67 eV to 2.25 eV).
The present disclosure describes a TWV fabrication method that overcomes complications with existing methods. The various advantages include the following:                1. when anti-reflective coating (ARC) is deposited, as part of routine solar cell fabrication, a pattern is added where the TWV is to be constructed, i.e. the ARC is used as a dielectric etch stop between the semiconductor and the metal pads on top of the wafer. This additional function of ARC simplifies TWV fabrication by eliminating the application of an extra etch stop;        2. standard manufacturing processing steps are employed, including photolithography, wet etching and thin film evaporation;        3. significant cost reduction due to the use of inexpensive equipment, chemicals and methods;        4. processing throughput is higher because multiple wafers can be etched at the same time and fewer etching process steps are required;        5. areas of wafer that need to be protected from etching can be protected by a photosensitive polymer, employing a lower cost material and simpler method than electroplating photoresist or electrografting;        6. smooth, 100% passivated TWV walls, which improves manufacturing yield by lowering the risk of device failure; and        7. a thinner substrate results from these processing steps, making the solar cells lighter and appropriate for space applications.        